The present invention relates to semiconductor analog switch circuits used as switch elements in a multiplexer circuit, for example.
Semiconductor analog switch circuits have been widely used as switch elements in digital circuits and analog circuits. A multiplexer circuit using the prior semiconductor analog switch circuits is illustrated in FIG. 1. In FIG. 1, reference numerals 11 and 12 designate semiconductor analog switch circuits. Inverters are denoted as 13 and 14 and a load capacitance as Co. The circuit of FIG. 1 operates in a sequence as shown in FIGS. 2A to 2C. When a switch drive signal CK1 becomes low (L), the potential of the output signal Vout is V1. When a switch drive signal CK2 becomes low, potential of the output signal Vout is V2. In this way, the semiconductor analog switch circuit under discussion operates to produce an output signal Vout, as shown in FIG. 2C.
The semiconductor analog switch circuits 11 and 12 in the multiplexer circuit shown in FIG. 1 are each made up of a P channel MOS transistor T.sub.P and an N channel MOS transistor T.sub.N, which are connected in parallel. As shown in an equivalent circuit of the switch circuit, (FIG. 3) a capacitance CmP is present between the gate and the source of the transistor T.sub.P and a capacitance CmN between the gate and the drain of the same transistor. These capacitances will be called mirror capacitances.
In the semiconductor analog switch circuits 11 and 12 thus arranged, an offset voltage .DELTA.V is produced at the output through the mirror capacitances CmP and CmN, when the clock pulse CK1 or CK2 changes from high to low level and vice versa. In a stationary level of the clock pulse CK1 or CK2, if the output voltage is Vo as shown in FIG. 4A, the output voltage is, as shown in FIG. 4B, sum of the output voltage Vo and the offset voltage .DELTA.V at the time of the level change of the clock pulse.
The charge conservation rule theoretically describes a relationship between a charge quantity when the clock pulse CK1 or CK2 is in a stationary state or in a stable level and a charge quantity immediately after the clock pulse has changed or is in a transient state: ##EQU1## Arranging the equation (1), we have the offset voltage .DELTA.V ##EQU2## Equations (1) and (2) hold on the assumption that the leak currents in the stationary state of the clock pulse and in the transient state are both negligible. Equation (1) indicates that if CmP.perspectiveto.CmN, the offset voltage .DELTA.V is substantially zero, and hence the output voltage is little influenced by the offset voltage.
The fabrication of the transistors T.sub.P and T.sub.N contains many process steps such as the step for registering a mask with a semiconductor substrate and the step for diffusing impurities into the semiconductor substrate. The process of the transistor fabrication is frequently accompanied by many problems. Misalignment of the mask with the semiconductor substrate results in nonregistration of patterns of the semiconductor layers. Nonuniformity of concentration of implanted impurities or a nonuniform heat treatment brings about nonuniform impurity diffusion. The expansion of a depletion layer, which occurs in the semiconductor device during its operation, is not uniform. Because of this, the above relation CmP.perspectiveto.CmN is frequently unsatisfied.
The mirror capacitances CmP and CmN will be described in relation to the noregistration in the pat- ternings.
FIGS. 5 and 6 illustrate semiconductor patterns of the semiconductor analog switch circuit 11 or 12 when the patterning is exactly done. The channel length (L) of the semiconductor structure with the pattern shown in FIG. 5 is oriented in the Y direction on the X-Y coordinates, and that of the semiconductor structure of FIG. 6 is oriented in the X direction.
In FIGS. 5 and 6, reference numerals 15 and 16 respectively designate a P channel MOS transistor and an N channel MOS transistor; 17, a gate electrode; 18, a contact hole; 19, a P.sup.+ diffusion layer; and 20, and N.sup.+ diffusion layer. The areas of overlapping portions designated as 21 and 22 equivalently correspond to the mirror capacitances CmP and CmN, respectively. Input and output electrodes are designated by reference numerals 23 and 24, respectively. Since the semiconductor devices shown in FIGS. 5 and 6 are patterned exactly as intended, their equivalent circuit is expressed as shown in FIG. 3. The semiconductor devices shown in FIGS. 5 and 6 satisfy the relationship CmP.perspectiveto.CmN and provide no offset voltage .DELTA.V when we consider only the patterning, but not if we consider the nonuniformity of the impurity concentration, the expansion of the depletion layer during the operation of the device, and the like.
FIGS. 7A and 8A illustrate two examples of the nonregistration of the pattern shown in FIG. 5. FIG. 7A shows an example where the electrode layers 17, 23 and 24 are displaced to the (+) side in the Y direction. FIG. 8A shows another example where these layers are displaced to the (-) side in the Y direction. The structure shown in FIG. 7A has an equivalent circuit as shown in FIG. 7B. The structure of FIG. 8A has an equivalent circuit as shown in FIG. 8B. As seen from FIGS. 7B and 8B, the equivalent circuits of the semiconductor structure with the patterns shown in FIGS. 7A and 8A are different from that of FIG. 3.
In the switch device with the FIG. 7A pattern, the capacitance disappears at the input, but is doubled (2CmP) at the output, when compared with the FIG. 3 circuit. Further, the capacitance CmN disappears at the output of the switch device, but is doubled at the input to have a value of 2CmN. In the switch device with the FIG. 8A pattern, unlike the FIG. 7 switch device, the doubled capacitance 2CmP appears at the input, but the capacitance of CmP disappears at the output. The capacitance of CmN disappears at the input but the 2CmN appears at the output.
FIGS. 9A and 9B illustrate two examples of the nonregistration or displacement of the patterns as shown in FIG. 6. In FIG. 9A the electrode layers 17, 23 and 24 are excessively displaced to the (+) side in the X direction. In FIG. 10A these layers 17, 23 and 24 are excessively displaced to the (-) side in the X direction. An equivalent circuit of the switch device with the FIG. 9A pattern is as shown in FIG. 9B. An equivalent circuit of the switch device with the FIG. 10A pattern is as shown in FIG. 10B.
In the case of the FIG. 9A pattern, both the capacitances CmP and CmN are not present at the input of the switch device, but 2CmP and 2CmN are present at, the output, as illustrated in the equivalent circuit of FIG. 9B. In the case of the FIG. 10A pattern, both 2CmP and 2CmN are present at the input, but none of these capacitances are present at the output, as shown in FIG. 10B.
When the pattern is not registered in the patterning, as shown in FIGS. 7A to 10A, the well balanced distribution of the mirror capacitances CmP and CmN at both the input and output, of the switch device, as shown in FIG. 3, is impaired. And in this case, these capacitances are only deviated to either the input or the output, as shown in FIGS. 7B to 10B. The result is generation of the offset voltage and variation of the output voltage. Thus, the output voltage produced is unreliable.
Another semiconductor analog switch circuit of the prior art is shown in FIG. 11. The analog switch circuit has a series circuit of P channel MOS transistors T.sub.P1 and T.sub.P2. A control signal CK is directly applied to the transistor T.sub.P1. An inverted control signal CK, formed by inverting the control signal CK by means of an inverter 25, is applied to the transistor T.sub.P2. A channel width ratio of these transistors is 2:1. Even if the switch circuit is so arranged, when the nonregistration or displacement of the patterns occurs in the patterning, the distribution of the mirror capacitors is not uniform at the input and output of the switch device, as shown in FIGS. 7A to 10B. This causes the output voltage of the switch circuit to vary. Therefore, an unreliable output voltage is also produced from the switch circuit.